Metric-Driven Verification Engineer at NXP Semiconductors

Metric-Driven Verification (MDV) was initially proposed by Cadence. It advocates a step-by-step approach starting from verification planning, constructing smart test benches with UVM methodology, executing regression, analyzing test results to finally feeding test results into the verification plan. It makes the verification task more manageable and the progress more clear to everyone. Next to that, with linking each test item to different metrics (test cases/functional coverage/checkers and assertions, etc), the total quality of verification is greatly improved. The objective is to extend this methodology to make it suited for a multi-vendor framework with as initial focus the use of VCS and Execution Manager. You will be part of an international team for the methodology development. You will closely interact with the Business Lines to ensure that the developed functionality meets the BL’s requirements while fitting the overall NXP strategy.
  • B.Tech/M.Tech in EE or Computer Science
  • Five years or more experience in IC design and verification
  • Basic knowledge of IC design
  • Basic knowledge on requirements management for IC design
  • Expert knowledge of verification tools such as VCS/Execution Manager and/or Xcelium/vManager.
  • Expert knowledge of verification methodologies such as the Universal Verification Methodology (UVM)
  • Good level of English is required (attendance to meetings / presentations with international team, reading and writing of documentation)
  • Capability to work in an international team, align to global needs while taking ownership of a sub-domain

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